1. Field of the Invention
The present invention relates generally to apparatus for protecting circuits from Electro Static Discharge (ESD) and, in particular, a network of snapback stages having controlled turnoff characteristics.
2. Description of Related Art
An integrated circuit may be subjected to an ESD event that can damage or destroy circuitry of the integrated circuit. Various types of ESD clamps have been devised which are typically connected in parallel to the circuitry to be protected and operate to shunt current around the circuitry to be protected during an ESD event. In order to provide effective protection while not interfering with the normal operation of the integrated circuit, the design of the ESD clamp must, among other things, take into account the breakdown voltage of the circuit to be protected and the normal operating voltage of the circuit. Normal operating voltages should not be sufficient to trigger the ESD clamp. Further, after the occurrence of an ESD event, the protection circuit should disengage, that is, unlatch, once normal operating voltages return.
FIG. 1 shows a conventional ESD protection or clamp circuit 10 connected to as to protect a exemplary circuit 14. Circuit 14 has, in the FIG. 1 example, an input connected to one integrated circuit pad 12A and a circuit common connected to another pad 12B. An ESD simulation circuit 16 is shown in accordance with the well-known Human Body Model (HBM) standard for simulating an ESD event produced by a human having a static charge. The HBM circuit includes a capacitor 18 of 100 picoFarads which is charged to approximately 5 kVolts. The charge on the capacitor 18 is transferred through a resistance 20 of 1.5 kΩ when the terminals 16A and 16B of the simulation circuit are applied to the pads 12A and 12B of the integrated circuit containing the circuit 14 to be protected. Assuming that the ESD protection circuit 10 is not present, the high voltage on the capacitor 18 will be applied directly to the input of the circuit 14. This high voltage will cause the input of circuit 14 to break down thereby causing current to flow though the circuit. If this current is limited to a short duration, circuit 14 will usually not be permanently damaged. However, unless steps are taken, the current will flow for a sufficient duration and magnitude to cause over heating of circuit 14 and permanent damage.
Referring to FIG. 2, a curve 22 is depicted that represents the voltage-current (V-I) characteristics of a typical ESD protection circuit 10, sometimes referred to as a snapback clamp. The primary objective of the ESD clamp circuit is to rapidly respond to an ESD event by shunting the large current (typically a few amperes) away from the circuit 14 to be protected so that any voltages generated in the circuit to be protected do not result in current flow through the circuit of sufficient magnitude to damage the circuit. Further, the ESD clamp circuit must not be triggered during normal operation and should unclamp at the end of the event so that normal operation can resume, as previously noted.
An ESD event will cause the voltage across the clamp circuit 10 and protected circuit 14 to rapidly increase. The ESD event is capable of producing a current having a magnitude of IESD, which can be as large as a few amperes. As the voltage across the ESD clamp 10 and the circuit 14 to be protected increases, the clamp will start to turn on significantly, that is trigger, at point 22A of curve 22. Clamp 10 is implemented so that the trigger point is below the breakdown voltage of circuit 14, although very short duration voltage peaks in excess of the circuit breakdown do not result in damage. The ESD clamp will then enter a negative resistance or snapback area of operation and will continue conducting an increasing current until the voltage across the clamp has been reduced to a holding voltage indicated by point 22B. The clamp current will ideally continue to increase until the current reaches the maximum current IESD at point 22C. If the maximum IESD current is too large for the clamp, the clamp will eventually reach a breakdown voltage at point 22D, with any additional current causing the clamp to be damaged or destroyed. Once the ESD event has ended, the ESD protection circuit 10 should unlatch thereby permitting normal operation of circuit 14.
Although there are a wide variety of circuits that can be used as ESD clamps, silicon controlled rectifiers (SCR) are frequently used for this application. FIGS. 3A and 3B depict one conventional implementation of an SCR type clamp circuit 10 commonly used in ESD applications. The FIG. 3A, 3B structure is sometimes called a low voltage triggered silicon controlled rectifier (LVTSCR). The exemplary LVTSCR if formed in a P type substrate 24. An N well 26 is formed in the substrate 24, with an N+ region 28 forming a contact to the N well. A P+ region 30 also formed in the N well 26, separated from the N+ region by a shallow trench isolation (sti) region 32A. An N+ extension 26A is formed near one end of the N well 26 and is separated from P+ region 30 by a further shallow trench isolation region 32B. N+ and P+ regions 28 and 30 are electrically interconnected by a metal track 34 (not shown in FIG. 3B), with this connection forming the anode terminal of the LTVSCR. As can best be seen in FIG. 3B, metal track 28 is electrically connected to N+ region 28 and P+ region 30 by way of a plurality of respective contact openings 26A and 30A formed in the oxide layer (not designated) disposed over those regions.
A further N+ region 36 is formed in the P substrate 24 and spaced apart from the extension 26A so as to form a channel region 24A intermediate the N+ regions 36 and 26A. A polysilicon gate 38 is disposed over the channel region 24A and is separated from the channel regions by a thin gate oxide (not designated). A P+ region 40 is formed in the P substrate 24 and separated from region 36 by a shallow trench isolation region 32C, with P+ region 40 forming a contact to the P substrate 24. P+ region 40 and N+ region 36 are connected together by a metal track 42 (not shown in FIG. 3B) which forms the cathode of the LVTSCR 10. Again as can best be seen in FIG. 3B, the metal track is electrically connected to N+ region 36 and P+ region 40 by way of a plurality of respective contact openings 36A and 40A formed in the oxide layer (not designated) disposed over those regions.
LVTSCR 10, as is the case for all SCR type structures, can be viewed as a PNP transistor merged with an NPN transistor, with the base of the PNP transistor and the collector of the PNP transistor being common and the collector of the PNP and the base of the NPN being common. P+ region 30, N well 26 and P substrate 24 forming the respective emitter, base and collector regions of the PNP device. The N well region 26 further defines a resistor having one terminal which is part of the base on the PNP and a second terminal which is connected to the emitter by way of N+ region 28 and metal track 34. The NPN device includes the N+ region 36, the P substrate 24 and the N well 26 which form the emitter, base and collector of the device. A resistor is formed in the P substrate 24, having one terminal that is part of the NPN base region and a second terminal connected to the emitter by way of P+ region 40 and metal track 42.
In operation, at the beginning of and ESD event, when the voltage is low, the PN junction between N well 26 and the P substrate 24 is slightly reversed biased. This reversed biased PN junction forms the common base-collector junction of the NPN and PNP devices. As the voltage increases, the leakage current increases when the PN junction begins avalanching. The junction voltage at which avalanching occurs is reduced by the highly doped N+ region 26A. The leakage current flows through the N well 26 resistor disposed between the base and emitter of the PNP thereby tending to turn on the PNP device. The current is enhanced by the nMOS transistor formed by drain region 26A, sometimes referred to as a floating drain, and source region 36. This nMOS transistor, which is effectively connected in parallel with the NPN transistor, will produce an added current though the N well resistor 26 thereby adding to the current that turns on the PNP transistor. The gate 38 is sometime referred to as the trigger input of the LVTSCR device. The turn on voltage or trigger voltage is represented by point 22A of FIG. 2.
Eventually, the increase in current in the PNP and NPN transistors will increase the current gain of the two devices so that each device will cause the other device to turn on. This regenerative SCR action will continue thereby reducing the voltage across the LVTSCR until the voltage drops to a holding voltage represented by point 22B of FIG. 2. As additional ESD current is conducted, the voltage across the LVTSCR will increase until the total IESD current is shunted through the device, as shown by point 22C of FIG. 2. Ideally, the device 10 has sufficient current conduction capability so that the voltage never reaches the thermal breakdown voltage of the represented by point 22D.
The threshold voltage of the LVTSCR can be adjusted by various means, including controlling the gate-source voltage of the nMOS transistor. Gate 32 could by grounded thereby producing a relatively high threshold voltage. A resistive divider can also be used to bias the gate voltage. Further, an RC network can be used, with a capacitor of suitable size connected between the gate 38 and anode 34 and a resistor of suitable size being connected between the gate 38 and the cathode 42. The RC circuit can also be formed by the parasitic capacitance of device 10 between the gate and anode so that only a gate to cathode resistor need by added to the device.
Although prior art ESD protection circuits, such as the LVTSCR 10 of FIGS. 3A and 3B, provide adequate circuit protection in many applications, it has been found that such circuits fail to adequately protect circuits 14 under various operating conditions. There is a need for ESD protection approaches that provide more adequate protection.